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<div class="title">xzdma_hw.h File Reference</div>  </div>
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Macros</h2></td></tr>
<tr class="memitem:ga7221416427c693436f444f4bf2d343ac"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__zdma__v1__0.html#ga7221416427c693436f444f4bf2d343ac">XZDMA_HW_H_</a></td></tr>
<tr class="memdesc:ga7221416427c693436f444f4bf2d343ac"><td class="mdescLeft">&#160;</td><td class="mdescRight">Prevent circular inclusions by using protection macros.  <a href="group__zdma__v1__0.html#ga7221416427c693436f444f4bf2d343ac">More...</a><br /></td></tr>
<tr class="separator:ga7221416427c693436f444f4bf2d343ac"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga3218611d01dec526018a6bd63dce603c"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__zdma__v1__0.html#ga3218611d01dec526018a6bd63dce603c">XZDma_In32</a>&#160;&#160;&#160;Xil_In32</td></tr>
<tr class="memdesc:ga3218611d01dec526018a6bd63dce603c"><td class="mdescLeft">&#160;</td><td class="mdescRight">Input operation.  <a href="group__zdma__v1__0.html#ga3218611d01dec526018a6bd63dce603c">More...</a><br /></td></tr>
<tr class="separator:ga3218611d01dec526018a6bd63dce603c"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga35a6987a4645af9cf6fc7463ca90f855"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__zdma__v1__0.html#ga35a6987a4645af9cf6fc7463ca90f855">XZDma_Out32</a>&#160;&#160;&#160;Xil_Out32</td></tr>
<tr class="memdesc:ga35a6987a4645af9cf6fc7463ca90f855"><td class="mdescLeft">&#160;</td><td class="mdescRight">Output operation.  <a href="group__zdma__v1__0.html#ga35a6987a4645af9cf6fc7463ca90f855">More...</a><br /></td></tr>
<tr class="separator:ga35a6987a4645af9cf6fc7463ca90f855"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gaf3bdd7a21f9d6add3ec23802122a7a85"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__zdma__v1__0.html#gaf3bdd7a21f9d6add3ec23802122a7a85">XZDma_ReadReg</a>(BaseAddress,  RegOffset)&#160;&#160;&#160;<a class="el" href="group__zdma__v1__0.html#ga3218611d01dec526018a6bd63dce603c">XZDma_In32</a>((BaseAddress) + (u32)(RegOffset))</td></tr>
<tr class="memdesc:gaf3bdd7a21f9d6add3ec23802122a7a85"><td class="mdescLeft">&#160;</td><td class="mdescRight">This macro reads the given register.  <a href="group__zdma__v1__0.html#gaf3bdd7a21f9d6add3ec23802122a7a85">More...</a><br /></td></tr>
<tr class="separator:gaf3bdd7a21f9d6add3ec23802122a7a85"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga1fe52ea6cc149bd35296d497837eff5b"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__zdma__v1__0.html#ga1fe52ea6cc149bd35296d497837eff5b">XZDma_WriteReg</a>(BaseAddress,  RegOffset,  Data)&#160;&#160;&#160;<a class="el" href="group__zdma__v1__0.html#ga35a6987a4645af9cf6fc7463ca90f855">XZDma_Out32</a>(((BaseAddress) + (u32)(RegOffset)), (u32)(Data))</td></tr>
<tr class="memdesc:ga1fe52ea6cc149bd35296d497837eff5b"><td class="mdescLeft">&#160;</td><td class="mdescRight">This macro writes the value into the given register.  <a href="group__zdma__v1__0.html#ga1fe52ea6cc149bd35296d497837eff5b">More...</a><br /></td></tr>
<tr class="separator:ga1fe52ea6cc149bd35296d497837eff5b"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr><td colspan="2"><div class="groupHeader">Registers offsets</div></td></tr>
<tr class="memitem:ga2e795eef49b7533e1fad1147cd4d32e2"><td class="memItemLeft" align="right" valign="top">
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XZDMA_ERR_CTRL</b>&#160;&#160;&#160;(0x000U)</td></tr>
<tr class="separator:ga2e795eef49b7533e1fad1147cd4d32e2"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga4eb1a3278c41660c45c98a912f3bb78c"><td class="memItemLeft" align="right" valign="top">
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XZDMA_CH_ECO</b>&#160;&#160;&#160;(0x004U)</td></tr>
<tr class="separator:ga4eb1a3278c41660c45c98a912f3bb78c"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gafebd4d2f0e07e0ec76efdfd9eefa5bcc"><td class="memItemLeft" align="right" valign="top">
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XZDMA_CH_ISR_OFFSET</b>&#160;&#160;&#160;(0x100U)</td></tr>
<tr class="separator:gafebd4d2f0e07e0ec76efdfd9eefa5bcc"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gad64ca368ca0a2555015a4b584af6f932"><td class="memItemLeft" align="right" valign="top">
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XZDMA_CH_IMR_OFFSET</b>&#160;&#160;&#160;(0x104U)</td></tr>
<tr class="separator:gad64ca368ca0a2555015a4b584af6f932"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga07ec911fddd8aac60dcf3f372f35a55f"><td class="memItemLeft" align="right" valign="top">
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XZDMA_CH_IEN_OFFSET</b>&#160;&#160;&#160;(0x108U)</td></tr>
<tr class="separator:ga07ec911fddd8aac60dcf3f372f35a55f"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga4289ae3cf905a7b910e225a826dcc092"><td class="memItemLeft" align="right" valign="top">
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XZDMA_CH_IDS_OFFSET</b>&#160;&#160;&#160;(0x10CU)</td></tr>
<tr class="separator:ga4289ae3cf905a7b910e225a826dcc092"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga4a136b2f8463361f6b1dfbb7f5a529c1"><td class="memItemLeft" align="right" valign="top">
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XZDMA_CH_CTRL0_OFFSET</b>&#160;&#160;&#160;(0x110U)</td></tr>
<tr class="separator:ga4a136b2f8463361f6b1dfbb7f5a529c1"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga37ac29f8d312223e1357d1682a9bb8f6"><td class="memItemLeft" align="right" valign="top">
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XZDMA_CH_CTRL1_OFFSET</b>&#160;&#160;&#160;(0x114U)</td></tr>
<tr class="separator:ga37ac29f8d312223e1357d1682a9bb8f6"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga09d02e009e3b1b334316006a36fea17d"><td class="memItemLeft" align="right" valign="top">
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XZDMA_CH_PERIF_OFFSET</b>&#160;&#160;&#160;(0x118U)</td></tr>
<tr class="separator:ga09d02e009e3b1b334316006a36fea17d"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gacf2c937862ebe510ca2a31cd62de3017"><td class="memItemLeft" align="right" valign="top">
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XZDMA_CH_STS_OFFSET</b>&#160;&#160;&#160;(0x11CU)</td></tr>
<tr class="separator:gacf2c937862ebe510ca2a31cd62de3017"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga9196e8301f49c2498a9035170f45def1"><td class="memItemLeft" align="right" valign="top">
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XZDMA_CH_DATA_ATTR_OFFSET</b>&#160;&#160;&#160;(0x120U)</td></tr>
<tr class="separator:ga9196e8301f49c2498a9035170f45def1"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gacbcc7d174206d2b6927fba4740183bce"><td class="memItemLeft" align="right" valign="top">
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XZDMA_CH_DSCR_ATTR_OFFSET</b>&#160;&#160;&#160;(0x124U)</td></tr>
<tr class="separator:gacbcc7d174206d2b6927fba4740183bce"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga3aa2f0fe4fc563f34c49689edf018302"><td class="memItemLeft" align="right" valign="top">
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XZDMA_CH_SRC_DSCR_WORD0_OFFSET</b>&#160;&#160;&#160;(0x128U)</td></tr>
<tr class="separator:ga3aa2f0fe4fc563f34c49689edf018302"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga64688f77cd5fec81da1973eff340e919"><td class="memItemLeft" align="right" valign="top">
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XZDMA_CH_SRC_DSCR_WORD1_OFFSET</b>&#160;&#160;&#160;(0x12CU)</td></tr>
<tr class="separator:ga64688f77cd5fec81da1973eff340e919"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gae18fd24798587afe61c205325eb6301d"><td class="memItemLeft" align="right" valign="top">
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XZDMA_CH_SRC_DSCR_WORD2_OFFSET</b>&#160;&#160;&#160;(0x130U)</td></tr>
<tr class="separator:gae18fd24798587afe61c205325eb6301d"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gab915c862c927027cd7dd25a8c42969d9"><td class="memItemLeft" align="right" valign="top">
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XZDMA_CH_SRC_DSCR_WORD3_OFFSET</b>&#160;&#160;&#160;(0x134U)</td></tr>
<tr class="separator:gab915c862c927027cd7dd25a8c42969d9"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga4fdd34e17d7abcc60475f81c0a7de6f4"><td class="memItemLeft" align="right" valign="top">
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XZDMA_CH_DST_DSCR_WORD0_OFFSET</b>&#160;&#160;&#160;(0x138U)</td></tr>
<tr class="separator:ga4fdd34e17d7abcc60475f81c0a7de6f4"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gaa062a8821ff410ea7a98e8c1e4eef87f"><td class="memItemLeft" align="right" valign="top">
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XZDMA_CH_DST_DSCR_WORD1_OFFSET</b>&#160;&#160;&#160;(0x13CU)</td></tr>
<tr class="separator:gaa062a8821ff410ea7a98e8c1e4eef87f"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga74352d16d6a3336ee60043e1253d9f47"><td class="memItemLeft" align="right" valign="top">
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XZDMA_CH_DST_DSCR_WORD2_OFFSET</b>&#160;&#160;&#160;(0x140U)</td></tr>
<tr class="separator:ga74352d16d6a3336ee60043e1253d9f47"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gabd326c9d0c1efa74ffbda717bf0cfefb"><td class="memItemLeft" align="right" valign="top">
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XZDMA_CH_DST_DSCR_WORD3_OFFSET</b>&#160;&#160;&#160;(0x144U)</td></tr>
<tr class="separator:gabd326c9d0c1efa74ffbda717bf0cfefb"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga9ba7c0a6aa5f518c15d9bec7f261a492"><td class="memItemLeft" align="right" valign="top">
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XZDMA_CH_WR_ONLY_WORD0_OFFSET</b>&#160;&#160;&#160;(0x148U)</td></tr>
<tr class="separator:ga9ba7c0a6aa5f518c15d9bec7f261a492"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga301b9fb0505f2b64c7a41d3c956de93f"><td class="memItemLeft" align="right" valign="top">
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XZDMA_CH_WR_ONLY_WORD1_OFFSET</b>&#160;&#160;&#160;(0x14CU)</td></tr>
<tr class="separator:ga301b9fb0505f2b64c7a41d3c956de93f"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga68220f8d3664c6012b808215eda04462"><td class="memItemLeft" align="right" valign="top">
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XZDMA_CH_WR_ONLY_WORD2_OFFSET</b>&#160;&#160;&#160;(0x150U)</td></tr>
<tr class="separator:ga68220f8d3664c6012b808215eda04462"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gadae78ae61707870b55b8b412768a1a37"><td class="memItemLeft" align="right" valign="top">
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XZDMA_CH_WR_ONLY_WORD3_OFFSET</b>&#160;&#160;&#160;(0x154U)</td></tr>
<tr class="separator:gadae78ae61707870b55b8b412768a1a37"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga9af56378e9c0989dc9fe35c8e85d2261"><td class="memItemLeft" align="right" valign="top">
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XZDMA_CH_SRC_START_LSB_OFFSET</b>&#160;&#160;&#160;(0x158U)</td></tr>
<tr class="separator:ga9af56378e9c0989dc9fe35c8e85d2261"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga98bffa226e8ece5bc195272d60b209b4"><td class="memItemLeft" align="right" valign="top">
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XZDMA_CH_SRC_START_MSB_OFFSET</b>&#160;&#160;&#160;(0x15CU)</td></tr>
<tr class="separator:ga98bffa226e8ece5bc195272d60b209b4"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga496651b7d9da3578eb51210f0466df68"><td class="memItemLeft" align="right" valign="top">
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XZDMA_CH_DST_START_LSB_OFFSET</b>&#160;&#160;&#160;(0x160U)</td></tr>
<tr class="separator:ga496651b7d9da3578eb51210f0466df68"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga599e6e7cedb027a4b49c3f406fe86add"><td class="memItemLeft" align="right" valign="top">
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XZDMA_CH_DST_START_MSB_OFFSET</b>&#160;&#160;&#160;(0x164U)</td></tr>
<tr class="separator:ga599e6e7cedb027a4b49c3f406fe86add"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga438955bc22a22c55b481e40e4f635809"><td class="memItemLeft" align="right" valign="top">
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XZDMA_CH_SRC_CUR_PYLD_LSB_OFFSET</b>&#160;&#160;&#160;(0x168U)</td></tr>
<tr class="separator:ga438955bc22a22c55b481e40e4f635809"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gacc6dc118b05c1c0ab02787d3de139e15"><td class="memItemLeft" align="right" valign="top">
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XZDMA_CH_SRC_CUR_PYLD_MSB_OFFSET</b>&#160;&#160;&#160;(0x16CU)</td></tr>
<tr class="separator:gacc6dc118b05c1c0ab02787d3de139e15"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga2cd0e4c651ffaeafe1990051b88ce016"><td class="memItemLeft" align="right" valign="top">
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XZDMA_CH_DST_CUR_PYLD_LSB_OFFSET</b>&#160;&#160;&#160;(0x170U)</td></tr>
<tr class="separator:ga2cd0e4c651ffaeafe1990051b88ce016"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga5d05b9255c5b779b608669bf9fae0ac4"><td class="memItemLeft" align="right" valign="top">
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XZDMA_CH_DST_CUR_PYLD_MSB_OFFSET</b>&#160;&#160;&#160;(0x174U)</td></tr>
<tr class="separator:ga5d05b9255c5b779b608669bf9fae0ac4"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga5c9dcfaacc2f1ef285ccb6e28826cd46"><td class="memItemLeft" align="right" valign="top">
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XZDMA_CH_SRC_CUR_DSCR_LSB_OFFSET</b>&#160;&#160;&#160;(0x178U)</td></tr>
<tr class="separator:ga5c9dcfaacc2f1ef285ccb6e28826cd46"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga5c2c55382cf4766ba3d4b0d35c32be85"><td class="memItemLeft" align="right" valign="top">
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XZDMA_CH_SRC_CUR_DSCR_MSB_OFFSET</b>&#160;&#160;&#160;(0x17CU)</td></tr>
<tr class="separator:ga5c2c55382cf4766ba3d4b0d35c32be85"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga2176641500144717c316406133cfac12"><td class="memItemLeft" align="right" valign="top">
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XZDMA_CH_DST_CUR_DSCR_LSB_OFFSET</b>&#160;&#160;&#160;(0x180U)</td></tr>
<tr class="separator:ga2176641500144717c316406133cfac12"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga534f29f951a3338d3d0d76e79c6fa4e3"><td class="memItemLeft" align="right" valign="top">
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XZDMA_CH_DST_CUR_DSCR_MSB_OFFSET</b>&#160;&#160;&#160;(0x184U)</td></tr>
<tr class="separator:ga534f29f951a3338d3d0d76e79c6fa4e3"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gade1e5356258bd5c5eafc876bed488e1a"><td class="memItemLeft" align="right" valign="top">
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XZDMA_CH_TOTAL_BYTE_OFFSET</b>&#160;&#160;&#160;(0x188U)</td></tr>
<tr class="separator:gade1e5356258bd5c5eafc876bed488e1a"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gafb2cdf2275f6f25e1d128f238fa7035e"><td class="memItemLeft" align="right" valign="top">
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XZDMA_CH_RATE_CNTL_OFFSET</b>&#160;&#160;&#160;(0x18CU)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XZDMA_CH_IRQ_SRC_ACCT_OFFSET</b>&#160;&#160;&#160;(0x190U)</td></tr>
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<tr class="memitem:gab3e42d0eaebdc47c69b0d07f66d6db4a"><td class="memItemLeft" align="right" valign="top">
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XZDMA_CH_IRQ_DST_ACCT_OFFSET</b>&#160;&#160;&#160;(0x194U)</td></tr>
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<tr class="memitem:ga26ee1ec7457309de7a3beecbad91c636"><td class="memItemLeft" align="right" valign="top">
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XZDMA_CH_CTRL2_OFFSET</b>&#160;&#160;&#160;(0x200U)</td></tr>
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<tr><td colspan="2"><div class="groupHeader">Interrupt Enable/Disable/Mask/Status registers bit masks and shifts</div></td></tr>
<tr class="memitem:ga749957c47c3d65c99861579af039b5db"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__zdma__v1__0.html#ga749957c47c3d65c99861579af039b5db">XZDMA_IXR_DMA_PAUSE_MASK</a>&#160;&#160;&#160;(0x00000800U)</td></tr>
<tr class="memdesc:ga749957c47c3d65c99861579af039b5db"><td class="mdescLeft">&#160;</td><td class="mdescRight">IXR pause mask.  <a href="group__zdma__v1__0.html#ga749957c47c3d65c99861579af039b5db">More...</a><br /></td></tr>
<tr class="separator:ga749957c47c3d65c99861579af039b5db"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga3427b844ce3c78c2e203cbe632ce8d11"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__zdma__v1__0.html#ga3427b844ce3c78c2e203cbe632ce8d11">XZDMA_IXR_DMA_DONE_MASK</a>&#160;&#160;&#160;(0x00000400U)</td></tr>
<tr class="memdesc:ga3427b844ce3c78c2e203cbe632ce8d11"><td class="mdescLeft">&#160;</td><td class="mdescRight">IXR done mask.  <a href="group__zdma__v1__0.html#ga3427b844ce3c78c2e203cbe632ce8d11">More...</a><br /></td></tr>
<tr class="separator:ga3427b844ce3c78c2e203cbe632ce8d11"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gaf54288858bd030f724d9939416975778"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__zdma__v1__0.html#gaf54288858bd030f724d9939416975778">XZDMA_IXR_AXI_WR_DATA_MASK</a>&#160;&#160;&#160;(0x00000200U)</td></tr>
<tr class="memdesc:gaf54288858bd030f724d9939416975778"><td class="mdescLeft">&#160;</td><td class="mdescRight">IXR AXI write data error mask.  <a href="group__zdma__v1__0.html#gaf54288858bd030f724d9939416975778">More...</a><br /></td></tr>
<tr class="separator:gaf54288858bd030f724d9939416975778"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gae24332b4ced51e3a17de66e87f508e72"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__zdma__v1__0.html#gae24332b4ced51e3a17de66e87f508e72">XZDMA_IXR_AXI_RD_DATA_MASK</a>&#160;&#160;&#160;(0x00000100U)</td></tr>
<tr class="memdesc:gae24332b4ced51e3a17de66e87f508e72"><td class="mdescLeft">&#160;</td><td class="mdescRight">IXR AXI read data error mask.  <a href="group__zdma__v1__0.html#gae24332b4ced51e3a17de66e87f508e72">More...</a><br /></td></tr>
<tr class="separator:gae24332b4ced51e3a17de66e87f508e72"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga508df1ddb568661acbe7eb02addd91aa"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__zdma__v1__0.html#ga508df1ddb568661acbe7eb02addd91aa">XZDMA_IXR_AXI_RD_DST_DSCR_MASK</a>&#160;&#160;&#160;(0x00000080U)</td></tr>
<tr class="memdesc:ga508df1ddb568661acbe7eb02addd91aa"><td class="mdescLeft">&#160;</td><td class="mdescRight">IXR AXI read descriptor error mask.  <a href="group__zdma__v1__0.html#ga508df1ddb568661acbe7eb02addd91aa">More...</a><br /></td></tr>
<tr class="separator:ga508df1ddb568661acbe7eb02addd91aa"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gaa616129e7e1d450c57a45518c883a4b0"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__zdma__v1__0.html#gaa616129e7e1d450c57a45518c883a4b0">XZDMA_IXR_AXI_RD_SRC_DSCR_MASK</a>&#160;&#160;&#160;(0x00000040U)</td></tr>
<tr class="memdesc:gaa616129e7e1d450c57a45518c883a4b0"><td class="mdescLeft">&#160;</td><td class="mdescRight">IXR AXI write descriptor error mask.  <a href="group__zdma__v1__0.html#gaa616129e7e1d450c57a45518c883a4b0">More...</a><br /></td></tr>
<tr class="separator:gaa616129e7e1d450c57a45518c883a4b0"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga063a0a10898da8f3c94a0aa9fadba651"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__zdma__v1__0.html#ga063a0a10898da8f3c94a0aa9fadba651">XZDMA_IXR_DST_ACCT_ERR_MASK</a>&#160;&#160;&#160;(0x00000020U)</td></tr>
<tr class="memdesc:ga063a0a10898da8f3c94a0aa9fadba651"><td class="mdescLeft">&#160;</td><td class="mdescRight">IXR DST interrupt count overflow mask.  <a href="group__zdma__v1__0.html#ga063a0a10898da8f3c94a0aa9fadba651">More...</a><br /></td></tr>
<tr class="separator:ga063a0a10898da8f3c94a0aa9fadba651"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gaeeea1f0a82eac76cd1dc511109f98981"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__zdma__v1__0.html#gaeeea1f0a82eac76cd1dc511109f98981">XZDMA_IXR_SRC_ACCT_ERR_MASK</a>&#160;&#160;&#160;(0x00000010U)</td></tr>
<tr class="memdesc:gaeeea1f0a82eac76cd1dc511109f98981"><td class="mdescLeft">&#160;</td><td class="mdescRight">IXR SRC interrupt count overflow mask.  <a href="group__zdma__v1__0.html#gaeeea1f0a82eac76cd1dc511109f98981">More...</a><br /></td></tr>
<tr class="separator:gaeeea1f0a82eac76cd1dc511109f98981"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gadc7f60924f5a890f36512209d386bbc4"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__zdma__v1__0.html#gadc7f60924f5a890f36512209d386bbc4">XZDMA_IXR_BYTE_CNT_OVRFL_MASK</a>&#160;&#160;&#160;(0x00000008U)</td></tr>
<tr class="memdesc:gadc7f60924f5a890f36512209d386bbc4"><td class="mdescLeft">&#160;</td><td class="mdescRight">IXR byte count over flow mask.  <a href="group__zdma__v1__0.html#gadc7f60924f5a890f36512209d386bbc4">More...</a><br /></td></tr>
<tr class="separator:gadc7f60924f5a890f36512209d386bbc4"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga3dd41eac3fa26888a9aa221b7b595c86"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__zdma__v1__0.html#ga3dd41eac3fa26888a9aa221b7b595c86">XZDMA_IXR_DST_DSCR_DONE_MASK</a>&#160;&#160;&#160;(0x00000004U)</td></tr>
<tr class="memdesc:ga3dd41eac3fa26888a9aa221b7b595c86"><td class="mdescLeft">&#160;</td><td class="mdescRight">IXR destination descriptor done mask.  <a href="group__zdma__v1__0.html#ga3dd41eac3fa26888a9aa221b7b595c86">More...</a><br /></td></tr>
<tr class="separator:ga3dd41eac3fa26888a9aa221b7b595c86"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga7c2d94ea3ac539c290ef339a08e92e39"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__zdma__v1__0.html#ga7c2d94ea3ac539c290ef339a08e92e39">XZDMA_IXR_SRC_DSCR_DONE_MASK</a>&#160;&#160;&#160;(0x00000002U)</td></tr>
<tr class="memdesc:ga7c2d94ea3ac539c290ef339a08e92e39"><td class="mdescLeft">&#160;</td><td class="mdescRight">IXR source descriptor done mask.  <a href="group__zdma__v1__0.html#ga7c2d94ea3ac539c290ef339a08e92e39">More...</a><br /></td></tr>
<tr class="separator:ga7c2d94ea3ac539c290ef339a08e92e39"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga1d088945acbf596b4b967fd8d88475db"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__zdma__v1__0.html#ga1d088945acbf596b4b967fd8d88475db">XZDMA_IXR_INV_APB_MASK</a>&#160;&#160;&#160;(0x00000001U)</td></tr>
<tr class="memdesc:ga1d088945acbf596b4b967fd8d88475db"><td class="mdescLeft">&#160;</td><td class="mdescRight">IXR invalid APB access mask.  <a href="group__zdma__v1__0.html#ga1d088945acbf596b4b967fd8d88475db">More...</a><br /></td></tr>
<tr class="separator:ga1d088945acbf596b4b967fd8d88475db"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gad82b072a8c2cc4c5e32fc43e9822e634"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__zdma__v1__0.html#gad82b072a8c2cc4c5e32fc43e9822e634">XZDMA_IXR_ALL_INTR_MASK</a>&#160;&#160;&#160;(0x00000FFFU)</td></tr>
<tr class="memdesc:gad82b072a8c2cc4c5e32fc43e9822e634"><td class="mdescLeft">&#160;</td><td class="mdescRight">IXR OR of all the interrupts mask.  <a href="group__zdma__v1__0.html#gad82b072a8c2cc4c5e32fc43e9822e634">More...</a><br /></td></tr>
<tr class="separator:gad82b072a8c2cc4c5e32fc43e9822e634"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga10a95a922410cd0599c744a1b17d568e"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__zdma__v1__0.html#ga10a95a922410cd0599c744a1b17d568e">XZDMA_IXR_DONE_MASK</a>&#160;&#160;&#160;(0x00000400U)</td></tr>
<tr class="memdesc:ga10a95a922410cd0599c744a1b17d568e"><td class="mdescLeft">&#160;</td><td class="mdescRight">IXR All done mask.  <a href="group__zdma__v1__0.html#ga10a95a922410cd0599c744a1b17d568e">More...</a><br /></td></tr>
<tr class="separator:ga10a95a922410cd0599c744a1b17d568e"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gaf2a5aa7481789b82f9a68ddbb803b072"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__zdma__v1__0.html#gaf2a5aa7481789b82f9a68ddbb803b072">XZDMA_IXR_ERR_MASK</a>&#160;&#160;&#160;(0x00000BF9U)</td></tr>
<tr class="memdesc:gaf2a5aa7481789b82f9a68ddbb803b072"><td class="mdescLeft">&#160;</td><td class="mdescRight">IXR all Error mask.  <a href="group__zdma__v1__0.html#gaf2a5aa7481789b82f9a68ddbb803b072">More...</a><br /></td></tr>
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<tr><td colspan="2"><div class="groupHeader">Channel Control0 register bit masks and shifts</div></td></tr>
<tr class="memitem:gac02824ee188615e27684eaea248c33eb"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__zdma__v1__0.html#gac02824ee188615e27684eaea248c33eb">XZDMA_CTRL0_OVR_FETCH_MASK</a>&#160;&#160;&#160;(0x00000080U)</td></tr>
<tr class="memdesc:gac02824ee188615e27684eaea248c33eb"><td class="mdescLeft">&#160;</td><td class="mdescRight">Over fetch mask.  <a href="group__zdma__v1__0.html#gac02824ee188615e27684eaea248c33eb">More...</a><br /></td></tr>
<tr class="separator:gac02824ee188615e27684eaea248c33eb"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gaadd46eb8217527c9907eced132dd50e1"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__zdma__v1__0.html#gaadd46eb8217527c9907eced132dd50e1">XZDMA_CTRL0_POINT_TYPE_MASK</a>&#160;&#160;&#160;(0x00000040U)</td></tr>
<tr class="memdesc:gaadd46eb8217527c9907eced132dd50e1"><td class="mdescLeft">&#160;</td><td class="mdescRight">Pointer type mask.  <a href="group__zdma__v1__0.html#gaadd46eb8217527c9907eced132dd50e1">More...</a><br /></td></tr>
<tr class="separator:gaadd46eb8217527c9907eced132dd50e1"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gaec1a986d8168e84618d9513a2c56541b"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__zdma__v1__0.html#gaec1a986d8168e84618d9513a2c56541b">XZDMA_CTRL0_MODE_MASK</a>&#160;&#160;&#160;(0x00000030U)</td></tr>
<tr class="memdesc:gaec1a986d8168e84618d9513a2c56541b"><td class="mdescLeft">&#160;</td><td class="mdescRight">Mode mask.  <a href="group__zdma__v1__0.html#gaec1a986d8168e84618d9513a2c56541b">More...</a><br /></td></tr>
<tr class="separator:gaec1a986d8168e84618d9513a2c56541b"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga1fc161baf17e0a6ba73942b50e0b2880"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__zdma__v1__0.html#ga1fc161baf17e0a6ba73942b50e0b2880">XZDMA_CTRL0_WRONLY_MASK</a>&#160;&#160;&#160;(0x00000010U)</td></tr>
<tr class="memdesc:ga1fc161baf17e0a6ba73942b50e0b2880"><td class="mdescLeft">&#160;</td><td class="mdescRight">Write only mask.  <a href="group__zdma__v1__0.html#ga1fc161baf17e0a6ba73942b50e0b2880">More...</a><br /></td></tr>
<tr class="separator:ga1fc161baf17e0a6ba73942b50e0b2880"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga4bb41a2cbf283dbbfdba7f9bc1f5bac3"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__zdma__v1__0.html#ga4bb41a2cbf283dbbfdba7f9bc1f5bac3">XZDMA_CTRL0_RDONLY_MASK</a>&#160;&#160;&#160;(0x00000020U)</td></tr>
<tr class="memdesc:ga4bb41a2cbf283dbbfdba7f9bc1f5bac3"><td class="mdescLeft">&#160;</td><td class="mdescRight">Read only mask.  <a href="group__zdma__v1__0.html#ga4bb41a2cbf283dbbfdba7f9bc1f5bac3">More...</a><br /></td></tr>
<tr class="separator:ga4bb41a2cbf283dbbfdba7f9bc1f5bac3"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga1a026580754e7de6e4305af5390959f7"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__zdma__v1__0.html#ga1a026580754e7de6e4305af5390959f7">XZDMA_CTRL0_RATE_CNTL_MASK</a>&#160;&#160;&#160;(0x00000008U)</td></tr>
<tr class="memdesc:ga1a026580754e7de6e4305af5390959f7"><td class="mdescLeft">&#160;</td><td class="mdescRight">Rate control mask.  <a href="group__zdma__v1__0.html#ga1a026580754e7de6e4305af5390959f7">More...</a><br /></td></tr>
<tr class="separator:ga1a026580754e7de6e4305af5390959f7"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga7eca536c9dac7c46bb03eadd6a391402"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__zdma__v1__0.html#ga7eca536c9dac7c46bb03eadd6a391402">XZDMA_CTRL0_CONT_ADDR_MASK</a>&#160;&#160;&#160;(0x00000004U)</td></tr>
<tr class="memdesc:ga7eca536c9dac7c46bb03eadd6a391402"><td class="mdescLeft">&#160;</td><td class="mdescRight">Continue address specified mask.  <a href="group__zdma__v1__0.html#ga7eca536c9dac7c46bb03eadd6a391402">More...</a><br /></td></tr>
<tr class="separator:ga7eca536c9dac7c46bb03eadd6a391402"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gaa10c98a9560919004f43cbcbe665b5b3"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__zdma__v1__0.html#gaa10c98a9560919004f43cbcbe665b5b3">XZDMA_CTRL0_CONT_MASK</a>&#160;&#160;&#160;(0x00000002U)</td></tr>
<tr class="memdesc:gaa10c98a9560919004f43cbcbe665b5b3"><td class="mdescLeft">&#160;</td><td class="mdescRight">Continue mask.  <a href="group__zdma__v1__0.html#gaa10c98a9560919004f43cbcbe665b5b3">More...</a><br /></td></tr>
<tr class="separator:gaa10c98a9560919004f43cbcbe665b5b3"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga076b5d95f700c212f10016db79d3099a"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__zdma__v1__0.html#ga076b5d95f700c212f10016db79d3099a">XZDMA_CTRL0_OVR_FETCH_SHIFT</a>&#160;&#160;&#160;(7U)</td></tr>
<tr class="memdesc:ga076b5d95f700c212f10016db79d3099a"><td class="mdescLeft">&#160;</td><td class="mdescRight">Over fetch shift.  <a href="group__zdma__v1__0.html#ga076b5d95f700c212f10016db79d3099a">More...</a><br /></td></tr>
<tr class="separator:ga076b5d95f700c212f10016db79d3099a"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga891c765b2004ba8b15018f99261a9ccb"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__zdma__v1__0.html#ga891c765b2004ba8b15018f99261a9ccb">XZDMA_CTRL0_POINT_TYPE_SHIFT</a>&#160;&#160;&#160;(6U)</td></tr>
<tr class="memdesc:ga891c765b2004ba8b15018f99261a9ccb"><td class="mdescLeft">&#160;</td><td class="mdescRight">Pointer type shift.  <a href="group__zdma__v1__0.html#ga891c765b2004ba8b15018f99261a9ccb">More...</a><br /></td></tr>
<tr class="separator:ga891c765b2004ba8b15018f99261a9ccb"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga66eaaf914136ac4eb5c4c758b4eea0ce"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__zdma__v1__0.html#ga66eaaf914136ac4eb5c4c758b4eea0ce">XZDMA_CTRL0_MODE_SHIFT</a>&#160;&#160;&#160;(4U)</td></tr>
<tr class="memdesc:ga66eaaf914136ac4eb5c4c758b4eea0ce"><td class="mdescLeft">&#160;</td><td class="mdescRight">Mode type shift.  <a href="group__zdma__v1__0.html#ga66eaaf914136ac4eb5c4c758b4eea0ce">More...</a><br /></td></tr>
<tr class="separator:ga66eaaf914136ac4eb5c4c758b4eea0ce"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gadb99cf87cd8081ab8195fafb44005d8d"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__zdma__v1__0.html#gadb99cf87cd8081ab8195fafb44005d8d">XZDMA_CTRL0_RESET_VALUE</a>&#160;&#160;&#160;(0x00000080U)</td></tr>
<tr class="memdesc:gadb99cf87cd8081ab8195fafb44005d8d"><td class="mdescLeft">&#160;</td><td class="mdescRight">CTRL0 reset value.  <a href="group__zdma__v1__0.html#gadb99cf87cd8081ab8195fafb44005d8d">More...</a><br /></td></tr>
<tr class="separator:gadb99cf87cd8081ab8195fafb44005d8d"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr><td colspan="2"><div class="groupHeader">Channel Control1 register bit masks and shifts</div></td></tr>
<tr class="memitem:ga4771477b0ae47b43caa80ce62cd5da26"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__zdma__v1__0.html#ga4771477b0ae47b43caa80ce62cd5da26">XZDMA_CTRL1_SRC_ISSUE_MASK</a>&#160;&#160;&#160;(0x0000001FU)</td></tr>
<tr class="memdesc:ga4771477b0ae47b43caa80ce62cd5da26"><td class="mdescLeft">&#160;</td><td class="mdescRight">Source issue mask.  <a href="group__zdma__v1__0.html#ga4771477b0ae47b43caa80ce62cd5da26">More...</a><br /></td></tr>
<tr class="separator:ga4771477b0ae47b43caa80ce62cd5da26"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gad1a614229d720d8abc65e98bba16def8"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__zdma__v1__0.html#gad1a614229d720d8abc65e98bba16def8">XZDMA_CTRL1_RESET_VALUE</a>&#160;&#160;&#160;(0x000003FFU)</td></tr>
<tr class="memdesc:gad1a614229d720d8abc65e98bba16def8"><td class="mdescLeft">&#160;</td><td class="mdescRight">CTRL1 reset value.  <a href="group__zdma__v1__0.html#gad1a614229d720d8abc65e98bba16def8">More...</a><br /></td></tr>
<tr class="separator:gad1a614229d720d8abc65e98bba16def8"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr><td colspan="2"><div class="groupHeader">Channel Peripheral register bit masks and shifts</div></td></tr>
<tr class="memitem:ga8348716bc8a747b60d1f8cd8451c6750"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__zdma__v1__0.html#ga8348716bc8a747b60d1f8cd8451c6750">XZDMA_PERIF_PROG_CELL_CNT_MASK</a>&#160;&#160;&#160;(0x0000003EU)</td></tr>
<tr class="memdesc:ga8348716bc8a747b60d1f8cd8451c6750"><td class="mdescLeft">&#160;</td><td class="mdescRight">Peripheral program cell count.  <a href="group__zdma__v1__0.html#ga8348716bc8a747b60d1f8cd8451c6750">More...</a><br /></td></tr>
<tr class="separator:ga8348716bc8a747b60d1f8cd8451c6750"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga63e0ec02ac5103d16e751d5bd4878177"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__zdma__v1__0.html#ga63e0ec02ac5103d16e751d5bd4878177">XZDMA_PERIF_SIDE_MASK</a>&#160;&#160;&#160;(0x00000002U)</td></tr>
<tr class="memdesc:ga63e0ec02ac5103d16e751d5bd4878177"><td class="mdescLeft">&#160;</td><td class="mdescRight">Interface attached the side mask.  <a href="group__zdma__v1__0.html#ga63e0ec02ac5103d16e751d5bd4878177">More...</a><br /></td></tr>
<tr class="separator:ga63e0ec02ac5103d16e751d5bd4878177"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gaaac5b3b9cef7eef0b1fcf253ad736314"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__zdma__v1__0.html#gaaac5b3b9cef7eef0b1fcf253ad736314">XZDMA_PERIF_EN_MASK</a>&#160;&#160;&#160;(0x00000001U)</td></tr>
<tr class="memdesc:gaaac5b3b9cef7eef0b1fcf253ad736314"><td class="mdescLeft">&#160;</td><td class="mdescRight">Peripheral flow control mask.  <a href="group__zdma__v1__0.html#gaaac5b3b9cef7eef0b1fcf253ad736314">More...</a><br /></td></tr>
<tr class="separator:gaaac5b3b9cef7eef0b1fcf253ad736314"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr><td colspan="2"><div class="groupHeader">Channel Status register bit masks and shifts</div></td></tr>
<tr class="memitem:ga26a7f12c178d08cf180df3a77dfa04c6"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__zdma__v1__0.html#ga26a7f12c178d08cf180df3a77dfa04c6">XZDMA_STS_DONE_ERR_MASK</a>&#160;&#160;&#160;(0x00000003U)</td></tr>
<tr class="memdesc:ga26a7f12c178d08cf180df3a77dfa04c6"><td class="mdescLeft">&#160;</td><td class="mdescRight">Done with errors mask.  <a href="group__zdma__v1__0.html#ga26a7f12c178d08cf180df3a77dfa04c6">More...</a><br /></td></tr>
<tr class="separator:ga26a7f12c178d08cf180df3a77dfa04c6"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga40cbf55c8d0f036f23a8a948a293b219"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__zdma__v1__0.html#ga40cbf55c8d0f036f23a8a948a293b219">XZDMA_STS_BUSY_MASK</a>&#160;&#160;&#160;(0x00000002U)</td></tr>
<tr class="memdesc:ga40cbf55c8d0f036f23a8a948a293b219"><td class="mdescLeft">&#160;</td><td class="mdescRight">ZDMA is busy in transfer mask.  <a href="group__zdma__v1__0.html#ga40cbf55c8d0f036f23a8a948a293b219">More...</a><br /></td></tr>
<tr class="separator:ga40cbf55c8d0f036f23a8a948a293b219"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gad902db953958b9834264c8f6801b0b27"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__zdma__v1__0.html#gad902db953958b9834264c8f6801b0b27">XZDMA_STS_PAUSE_MASK</a>&#160;&#160;&#160;(0x00000001U)</td></tr>
<tr class="memdesc:gad902db953958b9834264c8f6801b0b27"><td class="mdescLeft">&#160;</td><td class="mdescRight">ZDMA is in Pause state mask.  <a href="group__zdma__v1__0.html#gad902db953958b9834264c8f6801b0b27">More...</a><br /></td></tr>
<tr class="separator:gad902db953958b9834264c8f6801b0b27"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga98e3cde4448cc5bccfd0929889b78694"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__zdma__v1__0.html#ga98e3cde4448cc5bccfd0929889b78694">XZDMA_STS_DONE_MASK</a>&#160;&#160;&#160;(0x00000000U)</td></tr>
<tr class="memdesc:ga98e3cde4448cc5bccfd0929889b78694"><td class="mdescLeft">&#160;</td><td class="mdescRight">ZDMA done mask.  <a href="group__zdma__v1__0.html#ga98e3cde4448cc5bccfd0929889b78694">More...</a><br /></td></tr>
<tr class="separator:ga98e3cde4448cc5bccfd0929889b78694"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gad241ee38734a72209dee1fdd21cf573f"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__zdma__v1__0.html#gad241ee38734a72209dee1fdd21cf573f">XZDMA_STS_ALL_MASK</a>&#160;&#160;&#160;(0x00000003U)</td></tr>
<tr class="memdesc:gad241ee38734a72209dee1fdd21cf573f"><td class="mdescLeft">&#160;</td><td class="mdescRight">ZDMA status mask.  <a href="group__zdma__v1__0.html#gad241ee38734a72209dee1fdd21cf573f">More...</a><br /></td></tr>
<tr class="separator:gad241ee38734a72209dee1fdd21cf573f"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr><td colspan="2"><div class="groupHeader">Channel Data Attribute register bit masks and shifts</div></td></tr>
<tr class="memitem:gaa881506ca78408d01653104a4250ab0c"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__zdma__v1__0.html#gaa881506ca78408d01653104a4250ab0c">XZDMA_DATA_ATTR_ARBURST_MASK</a>&#160;&#160;&#160;(0x0C000000U)</td></tr>
<tr class="memdesc:gaa881506ca78408d01653104a4250ab0c"><td class="mdescLeft">&#160;</td><td class="mdescRight">Data ArBurst mask.  <a href="group__zdma__v1__0.html#gaa881506ca78408d01653104a4250ab0c">More...</a><br /></td></tr>
<tr class="separator:gaa881506ca78408d01653104a4250ab0c"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga1c99701981861114d5e4d470728b4fbe"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__zdma__v1__0.html#ga1c99701981861114d5e4d470728b4fbe">XZDMA_DATA_ATTR_ARCACHE_MASK</a>&#160;&#160;&#160;(0x03C00000U)</td></tr>
<tr class="memdesc:ga1c99701981861114d5e4d470728b4fbe"><td class="mdescLeft">&#160;</td><td class="mdescRight">Data ArCache mask.  <a href="group__zdma__v1__0.html#ga1c99701981861114d5e4d470728b4fbe">More...</a><br /></td></tr>
<tr class="separator:ga1c99701981861114d5e4d470728b4fbe"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga38b5f7ce878bbea9db766a8a7b2c315b"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__zdma__v1__0.html#ga38b5f7ce878bbea9db766a8a7b2c315b">XZDMA_DATA_ATTR_ARQOS_MASK</a>&#160;&#160;&#160;(0x003C0000U)</td></tr>
<tr class="memdesc:ga38b5f7ce878bbea9db766a8a7b2c315b"><td class="mdescLeft">&#160;</td><td class="mdescRight">Data ARQos masks.  <a href="group__zdma__v1__0.html#ga38b5f7ce878bbea9db766a8a7b2c315b">More...</a><br /></td></tr>
<tr class="separator:ga38b5f7ce878bbea9db766a8a7b2c315b"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga07bd79ddfdc6aae7c165b7650f84256c"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__zdma__v1__0.html#ga07bd79ddfdc6aae7c165b7650f84256c">XZDMA_DATA_ATTR_ARLEN_MASK</a>&#160;&#160;&#160;(0x0003C000U)</td></tr>
<tr class="memdesc:ga07bd79ddfdc6aae7c165b7650f84256c"><td class="mdescLeft">&#160;</td><td class="mdescRight">Data Arlen mask.  <a href="group__zdma__v1__0.html#ga07bd79ddfdc6aae7c165b7650f84256c">More...</a><br /></td></tr>
<tr class="separator:ga07bd79ddfdc6aae7c165b7650f84256c"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gacd98a78505f4b50ccf9bcee2cf4d4217"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__zdma__v1__0.html#gacd98a78505f4b50ccf9bcee2cf4d4217">XZDMA_DATA_ATTR_AWBURST_MASK</a>&#160;&#160;&#160;(0x00003000U)</td></tr>
<tr class="memdesc:gacd98a78505f4b50ccf9bcee2cf4d4217"><td class="mdescLeft">&#160;</td><td class="mdescRight">Data Awburst mask.  <a href="group__zdma__v1__0.html#gacd98a78505f4b50ccf9bcee2cf4d4217">More...</a><br /></td></tr>
<tr class="separator:gacd98a78505f4b50ccf9bcee2cf4d4217"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga4dea58f251b7ccea5ea60374edec3c7d"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__zdma__v1__0.html#ga4dea58f251b7ccea5ea60374edec3c7d">XZDMA_DATA_ATTR_AWCACHE_MASK</a>&#160;&#160;&#160;(0x00000F00U)</td></tr>
<tr class="memdesc:ga4dea58f251b7ccea5ea60374edec3c7d"><td class="mdescLeft">&#160;</td><td class="mdescRight">Data AwCache mask.  <a href="group__zdma__v1__0.html#ga4dea58f251b7ccea5ea60374edec3c7d">More...</a><br /></td></tr>
<tr class="separator:ga4dea58f251b7ccea5ea60374edec3c7d"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gaa7a54821c20e9a7e23252a5ec971c5bd"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__zdma__v1__0.html#gaa7a54821c20e9a7e23252a5ec971c5bd">XZDMA_DATA_ATTR_AWQOS_MASK</a>&#160;&#160;&#160;(0x000000F0U)</td></tr>
<tr class="memdesc:gaa7a54821c20e9a7e23252a5ec971c5bd"><td class="mdescLeft">&#160;</td><td class="mdescRight">Data AwQos mask.  <a href="group__zdma__v1__0.html#gaa7a54821c20e9a7e23252a5ec971c5bd">More...</a><br /></td></tr>
<tr class="separator:gaa7a54821c20e9a7e23252a5ec971c5bd"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga89ab3c509042ce8ddd0fec5c83a8bc8b"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__zdma__v1__0.html#ga89ab3c509042ce8ddd0fec5c83a8bc8b">XZDMA_DATA_ATTR_AWLEN_MASK</a>&#160;&#160;&#160;(0x0000000FU)</td></tr>
<tr class="memdesc:ga89ab3c509042ce8ddd0fec5c83a8bc8b"><td class="mdescLeft">&#160;</td><td class="mdescRight">Data Awlen mask.  <a href="group__zdma__v1__0.html#ga89ab3c509042ce8ddd0fec5c83a8bc8b">More...</a><br /></td></tr>
<tr class="separator:ga89ab3c509042ce8ddd0fec5c83a8bc8b"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gaefa353e6b08ee707e01d99d1c45be931"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__zdma__v1__0.html#gaefa353e6b08ee707e01d99d1c45be931">XZDMA_DATA_ATTR_ARBURST_SHIFT</a>&#160;&#160;&#160;(26U)</td></tr>
<tr class="memdesc:gaefa353e6b08ee707e01d99d1c45be931"><td class="mdescLeft">&#160;</td><td class="mdescRight">Data Arburst shift.  <a href="group__zdma__v1__0.html#gaefa353e6b08ee707e01d99d1c45be931">More...</a><br /></td></tr>
<tr class="separator:gaefa353e6b08ee707e01d99d1c45be931"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga3fe36e16ad31159f99a640e9c3bb6568"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__zdma__v1__0.html#ga3fe36e16ad31159f99a640e9c3bb6568">XZDMA_DATA_ATTR_ARCACHE_SHIFT</a>&#160;&#160;&#160;(22U)</td></tr>
<tr class="memdesc:ga3fe36e16ad31159f99a640e9c3bb6568"><td class="mdescLeft">&#160;</td><td class="mdescRight">Data ArCache shift.  <a href="group__zdma__v1__0.html#ga3fe36e16ad31159f99a640e9c3bb6568">More...</a><br /></td></tr>
<tr class="separator:ga3fe36e16ad31159f99a640e9c3bb6568"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gaf3d3eac7b0b5139637930e1d58775d2b"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__zdma__v1__0.html#gaf3d3eac7b0b5139637930e1d58775d2b">XZDMA_DATA_ATTR_ARQOS_SHIFT</a>&#160;&#160;&#160;(18U)</td></tr>
<tr class="memdesc:gaf3d3eac7b0b5139637930e1d58775d2b"><td class="mdescLeft">&#160;</td><td class="mdescRight">Data ARQos shift.  <a href="group__zdma__v1__0.html#gaf3d3eac7b0b5139637930e1d58775d2b">More...</a><br /></td></tr>
<tr class="separator:gaf3d3eac7b0b5139637930e1d58775d2b"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gad57774673e1e4297dada019e7a1351a0"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__zdma__v1__0.html#gad57774673e1e4297dada019e7a1351a0">XZDMA_DATA_ATTR_ARLEN_SHIFT</a>&#160;&#160;&#160;(14U)</td></tr>
<tr class="memdesc:gad57774673e1e4297dada019e7a1351a0"><td class="mdescLeft">&#160;</td><td class="mdescRight">Data Arlen shift.  <a href="group__zdma__v1__0.html#gad57774673e1e4297dada019e7a1351a0">More...</a><br /></td></tr>
<tr class="separator:gad57774673e1e4297dada019e7a1351a0"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga7002622e4bf8c047681ebe4b0efdedc7"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__zdma__v1__0.html#ga7002622e4bf8c047681ebe4b0efdedc7">XZDMA_DATA_ATTR_AWBURST_SHIFT</a>&#160;&#160;&#160;(12U)</td></tr>
<tr class="memdesc:ga7002622e4bf8c047681ebe4b0efdedc7"><td class="mdescLeft">&#160;</td><td class="mdescRight">Data Awburst shift.  <a href="group__zdma__v1__0.html#ga7002622e4bf8c047681ebe4b0efdedc7">More...</a><br /></td></tr>
<tr class="separator:ga7002622e4bf8c047681ebe4b0efdedc7"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga0320f84e12d6075b163f5adf415496fc"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__zdma__v1__0.html#ga0320f84e12d6075b163f5adf415496fc">XZDMA_DATA_ATTR_AWCACHE_SHIFT</a>&#160;&#160;&#160;(8U)</td></tr>
<tr class="memdesc:ga0320f84e12d6075b163f5adf415496fc"><td class="mdescLeft">&#160;</td><td class="mdescRight">Data Awcache shift.  <a href="group__zdma__v1__0.html#ga0320f84e12d6075b163f5adf415496fc">More...</a><br /></td></tr>
<tr class="separator:ga0320f84e12d6075b163f5adf415496fc"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gab5a55d0a765874f387e853cfebaa48a7"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__zdma__v1__0.html#gab5a55d0a765874f387e853cfebaa48a7">XZDMA_DATA_ATTR_AWQOS_SHIFT</a>&#160;&#160;&#160;(4U)</td></tr>
<tr class="memdesc:gab5a55d0a765874f387e853cfebaa48a7"><td class="mdescLeft">&#160;</td><td class="mdescRight">Data Awqos shift.  <a href="group__zdma__v1__0.html#gab5a55d0a765874f387e853cfebaa48a7">More...</a><br /></td></tr>
<tr class="separator:gab5a55d0a765874f387e853cfebaa48a7"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga6fc39f50cddb793d1ffa51bf3b36e471"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__zdma__v1__0.html#ga6fc39f50cddb793d1ffa51bf3b36e471">XZDMA_DATA_ATTR_RESET_VALUE</a>&#160;&#160;&#160;(0x0483D20FU)</td></tr>
<tr class="memdesc:ga6fc39f50cddb793d1ffa51bf3b36e471"><td class="mdescLeft">&#160;</td><td class="mdescRight">Data Attributes reset value.  <a href="group__zdma__v1__0.html#ga6fc39f50cddb793d1ffa51bf3b36e471">More...</a><br /></td></tr>
<tr class="separator:ga6fc39f50cddb793d1ffa51bf3b36e471"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr><td colspan="2"><div class="groupHeader">Channel DSCR Attribute register bit masks and shifts</div></td></tr>
<tr class="memitem:ga0c761d93384a2590517648a21792a938"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__zdma__v1__0.html#ga0c761d93384a2590517648a21792a938">XZDMA_DSCR_ATTR_AXCOHRNT_MASK</a>&#160;&#160;&#160;(0x00000100U)</td></tr>
<tr class="memdesc:ga0c761d93384a2590517648a21792a938"><td class="mdescLeft">&#160;</td><td class="mdescRight">Descriptor coherent mask.  <a href="group__zdma__v1__0.html#ga0c761d93384a2590517648a21792a938">More...</a><br /></td></tr>
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<tr class="memitem:gabc067f3d88ea147d23f49168fc3f7de6"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__zdma__v1__0.html#gabc067f3d88ea147d23f49168fc3f7de6">XZDMA_DSCR_ATTR_AXCACHE_MASK</a>&#160;&#160;&#160;(0x000000F0U)</td></tr>
<tr class="memdesc:gabc067f3d88ea147d23f49168fc3f7de6"><td class="mdescLeft">&#160;</td><td class="mdescRight">Descriptor cache mask.  <a href="group__zdma__v1__0.html#gabc067f3d88ea147d23f49168fc3f7de6">More...</a><br /></td></tr>
<tr class="separator:gabc067f3d88ea147d23f49168fc3f7de6"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gab1f6da6a358a3f6c721b9fccabc6b4d1"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__zdma__v1__0.html#gab1f6da6a358a3f6c721b9fccabc6b4d1">XZDMA_DSCR_ATTR_AXQOS_MASK</a>&#160;&#160;&#160;(0x0000000FU)</td></tr>
<tr class="memdesc:gab1f6da6a358a3f6c721b9fccabc6b4d1"><td class="mdescLeft">&#160;</td><td class="mdescRight">Descriptor AxQos mask.  <a href="group__zdma__v1__0.html#gab1f6da6a358a3f6c721b9fccabc6b4d1">More...</a><br /></td></tr>
<tr class="separator:gab1f6da6a358a3f6c721b9fccabc6b4d1"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gacf85276abd3537f849cb9279861570a4"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__zdma__v1__0.html#gacf85276abd3537f849cb9279861570a4">XZDMA_DSCR_ATTR_AXCOHRNT_SHIFT</a>&#160;&#160;&#160;(8U)</td></tr>
<tr class="memdesc:gacf85276abd3537f849cb9279861570a4"><td class="mdescLeft">&#160;</td><td class="mdescRight">Descriptor coherent shift.  <a href="group__zdma__v1__0.html#gacf85276abd3537f849cb9279861570a4">More...</a><br /></td></tr>
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<tr class="memitem:ga6cae905057544443789c744ace6b7700"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__zdma__v1__0.html#ga6cae905057544443789c744ace6b7700">XZDMA_DSCR_ATTR_AXCACHE_SHIFT</a>&#160;&#160;&#160;(7U)</td></tr>
<tr class="memdesc:ga6cae905057544443789c744ace6b7700"><td class="mdescLeft">&#160;</td><td class="mdescRight">Descriptor cache shift.  <a href="group__zdma__v1__0.html#ga6cae905057544443789c744ace6b7700">More...</a><br /></td></tr>
<tr class="separator:ga6cae905057544443789c744ace6b7700"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gaeb9a7bdb3c0b6be0adf689c98e0526c3"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__zdma__v1__0.html#gaeb9a7bdb3c0b6be0adf689c98e0526c3">XZDMA_DSCR_ATTR_RESET_VALUE</a>&#160;&#160;&#160;(0x00000000U)</td></tr>
<tr class="memdesc:gaeb9a7bdb3c0b6be0adf689c98e0526c3"><td class="mdescLeft">&#160;</td><td class="mdescRight">Dscr Attributes reset value.  <a href="group__zdma__v1__0.html#gaeb9a7bdb3c0b6be0adf689c98e0526c3">More...</a><br /></td></tr>
<tr class="separator:gaeb9a7bdb3c0b6be0adf689c98e0526c3"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr><td colspan="2"><div class="groupHeader">Channel Source/Destination Word0 register bit mask</div></td></tr>
<tr class="memitem:gad1af37520a9ff8f0b18ae5cb2af2f9f4"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__zdma__v1__0.html#gad1af37520a9ff8f0b18ae5cb2af2f9f4">XZDMA_WORD0_LSB_MASK</a>&#160;&#160;&#160;(0xFFFFFFFFU)</td></tr>
<tr class="memdesc:gad1af37520a9ff8f0b18ae5cb2af2f9f4"><td class="mdescLeft">&#160;</td><td class="mdescRight">LSB Address mask.  <a href="group__zdma__v1__0.html#gad1af37520a9ff8f0b18ae5cb2af2f9f4">More...</a><br /></td></tr>
<tr class="separator:gad1af37520a9ff8f0b18ae5cb2af2f9f4"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr><td colspan="2"><div class="groupHeader">Channel Source/Destination Word1 register bit mask</div></td></tr>
<tr class="memitem:gac8bb93895e5f91a7c3133e1cf3f51cf0"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__zdma__v1__0.html#gac8bb93895e5f91a7c3133e1cf3f51cf0">XZDMA_WORD1_MSB_MASK</a>&#160;&#160;&#160;(0x0001FFFFU)</td></tr>
<tr class="memdesc:gac8bb93895e5f91a7c3133e1cf3f51cf0"><td class="mdescLeft">&#160;</td><td class="mdescRight">MSB Address mask.  <a href="group__zdma__v1__0.html#gac8bb93895e5f91a7c3133e1cf3f51cf0">More...</a><br /></td></tr>
<tr class="separator:gac8bb93895e5f91a7c3133e1cf3f51cf0"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga055f4c7ad4789221cc57f6006e616d7f"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__zdma__v1__0.html#ga055f4c7ad4789221cc57f6006e616d7f">XZDMA_WORD1_MSB_SHIFT</a>&#160;&#160;&#160;(32U)</td></tr>
<tr class="memdesc:ga055f4c7ad4789221cc57f6006e616d7f"><td class="mdescLeft">&#160;</td><td class="mdescRight">MSB Address shift.  <a href="group__zdma__v1__0.html#ga055f4c7ad4789221cc57f6006e616d7f">More...</a><br /></td></tr>
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<tr><td colspan="2"><div class="groupHeader">Channel Source/Destination Word2 register bit mask</div></td></tr>
<tr class="memitem:ga806daa6c38fb4441e8031789784b89b3"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__zdma__v1__0.html#ga806daa6c38fb4441e8031789784b89b3">XZDMA_WORD2_SIZE_MASK</a>&#160;&#160;&#160;(0x3FFFFFFFU)</td></tr>
<tr class="memdesc:ga806daa6c38fb4441e8031789784b89b3"><td class="mdescLeft">&#160;</td><td class="mdescRight">Size mask.  <a href="group__zdma__v1__0.html#ga806daa6c38fb4441e8031789784b89b3">More...</a><br /></td></tr>
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<tr><td colspan="2"><div class="groupHeader">Channel Source/Destination Word3 register bit masks and shifts</div></td></tr>
<tr class="memitem:ga8485f09f7b5e6c611b533862b4023860"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__zdma__v1__0.html#ga8485f09f7b5e6c611b533862b4023860">XZDMA_WORD3_CMD_MASK</a>&#160;&#160;&#160;(0x00000018U)</td></tr>
<tr class="memdesc:ga8485f09f7b5e6c611b533862b4023860"><td class="mdescLeft">&#160;</td><td class="mdescRight">Cmd mask.  <a href="group__zdma__v1__0.html#ga8485f09f7b5e6c611b533862b4023860">More...</a><br /></td></tr>
<tr class="separator:ga8485f09f7b5e6c611b533862b4023860"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga93e3bffa167d70e2f56c8e93d114d335"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__zdma__v1__0.html#ga93e3bffa167d70e2f56c8e93d114d335">XZDMA_WORD3_CMD_SHIFT</a>&#160;&#160;&#160;(3U)</td></tr>
<tr class="memdesc:ga93e3bffa167d70e2f56c8e93d114d335"><td class="mdescLeft">&#160;</td><td class="mdescRight">Cmd shift.  <a href="group__zdma__v1__0.html#ga93e3bffa167d70e2f56c8e93d114d335">More...</a><br /></td></tr>
<tr class="separator:ga93e3bffa167d70e2f56c8e93d114d335"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gacf5d8cf4ecff1be0f2dacfa5fb90c8d9"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__zdma__v1__0.html#gacf5d8cf4ecff1be0f2dacfa5fb90c8d9">XZDMA_WORD3_CMD_NXTVALID_MASK</a>&#160;&#160;&#160;(0x00000000U)</td></tr>
<tr class="memdesc:gacf5d8cf4ecff1be0f2dacfa5fb90c8d9"><td class="mdescLeft">&#160;</td><td class="mdescRight">Next Dscr is valid mask.  <a href="group__zdma__v1__0.html#gacf5d8cf4ecff1be0f2dacfa5fb90c8d9">More...</a><br /></td></tr>
<tr class="separator:gacf5d8cf4ecff1be0f2dacfa5fb90c8d9"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga68ef623af6d8fe3215167f134daae66c"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__zdma__v1__0.html#ga68ef623af6d8fe3215167f134daae66c">XZDMA_WORD3_CMD_PAUSE_MASK</a>&#160;&#160;&#160;(0x00000008U)</td></tr>
<tr class="memdesc:ga68ef623af6d8fe3215167f134daae66c"><td class="mdescLeft">&#160;</td><td class="mdescRight">Pause after this dscr mask.  <a href="group__zdma__v1__0.html#ga68ef623af6d8fe3215167f134daae66c">More...</a><br /></td></tr>
<tr class="separator:ga68ef623af6d8fe3215167f134daae66c"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga0ec4db1fe53ded3ce7696e291b5188c2"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__zdma__v1__0.html#ga0ec4db1fe53ded3ce7696e291b5188c2">XZDMA_WORD3_CMD_STOP_MASK</a>&#160;&#160;&#160;(0x00000010U)</td></tr>
<tr class="memdesc:ga0ec4db1fe53ded3ce7696e291b5188c2"><td class="mdescLeft">&#160;</td><td class="mdescRight">Stop after this ..* dscr mask.  <a href="group__zdma__v1__0.html#ga0ec4db1fe53ded3ce7696e291b5188c2">More...</a><br /></td></tr>
<tr class="separator:ga0ec4db1fe53ded3ce7696e291b5188c2"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gaf7a5b80dbf16443b2f9b0247f7da946d"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__zdma__v1__0.html#gaf7a5b80dbf16443b2f9b0247f7da946d">XZDMA_WORD3_INTR_MASK</a>&#160;&#160;&#160;(0x00000004U)</td></tr>
<tr class="memdesc:gaf7a5b80dbf16443b2f9b0247f7da946d"><td class="mdescLeft">&#160;</td><td class="mdescRight">Interrupt enable or disable mask.  <a href="group__zdma__v1__0.html#gaf7a5b80dbf16443b2f9b0247f7da946d">More...</a><br /></td></tr>
<tr class="separator:gaf7a5b80dbf16443b2f9b0247f7da946d"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga482e905a7456e30f19e0a6b465e4f591"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__zdma__v1__0.html#ga482e905a7456e30f19e0a6b465e4f591">XZDMA_WORD3_INTR_SHIFT</a>&#160;&#160;&#160;(2U)</td></tr>
<tr class="memdesc:ga482e905a7456e30f19e0a6b465e4f591"><td class="mdescLeft">&#160;</td><td class="mdescRight">Interrupt enable disable shift.  <a href="group__zdma__v1__0.html#ga482e905a7456e30f19e0a6b465e4f591">More...</a><br /></td></tr>
<tr class="separator:ga482e905a7456e30f19e0a6b465e4f591"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga993831fb92a5b1b006e16fe087fd1b85"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__zdma__v1__0.html#ga993831fb92a5b1b006e16fe087fd1b85">XZDMA_WORD3_TYPE_MASK</a>&#160;&#160;&#160;(0x00000002U)</td></tr>
<tr class="memdesc:ga993831fb92a5b1b006e16fe087fd1b85"><td class="mdescLeft">&#160;</td><td class="mdescRight">Type of Descriptor mask.  <a href="group__zdma__v1__0.html#ga993831fb92a5b1b006e16fe087fd1b85">More...</a><br /></td></tr>
<tr class="separator:ga993831fb92a5b1b006e16fe087fd1b85"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga69cfbc1e5425c35ed1bd98376cedc61a"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__zdma__v1__0.html#ga69cfbc1e5425c35ed1bd98376cedc61a">XZDMA_WORD3_TYPE_SHIFT</a>&#160;&#160;&#160;(1U)</td></tr>
<tr class="memdesc:ga69cfbc1e5425c35ed1bd98376cedc61a"><td class="mdescLeft">&#160;</td><td class="mdescRight">Type of Descriptor Shift.  <a href="group__zdma__v1__0.html#ga69cfbc1e5425c35ed1bd98376cedc61a">More...</a><br /></td></tr>
<tr class="separator:ga69cfbc1e5425c35ed1bd98376cedc61a"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gac2aeec8d3bc367ed78ec8a2436f780a7"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__zdma__v1__0.html#gac2aeec8d3bc367ed78ec8a2436f780a7">XZDMA_WORD3_COHRNT_MASK</a>&#160;&#160;&#160;(0x00000001U)</td></tr>
<tr class="memdesc:gac2aeec8d3bc367ed78ec8a2436f780a7"><td class="mdescLeft">&#160;</td><td class="mdescRight">Coherence mask.  <a href="group__zdma__v1__0.html#gac2aeec8d3bc367ed78ec8a2436f780a7">More...</a><br /></td></tr>
<tr class="separator:gac2aeec8d3bc367ed78ec8a2436f780a7"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr><td colspan="2"><div class="groupHeader">Channel Source/Destination start address or current payload</div></td></tr>
<tr><td colspan="2"><div class="groupText"><p>MSB register bit mask </p>
</div></td></tr>
<tr class="memitem:ga8b4169e9fb49a54f7c287d6ae3e57654"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__zdma__v1__0.html#ga8b4169e9fb49a54f7c287d6ae3e57654">XZDMA_START_MSB_ADDR_MASK</a>&#160;&#160;&#160;(0x0001FFFFU)</td></tr>
<tr class="memdesc:ga8b4169e9fb49a54f7c287d6ae3e57654"><td class="mdescLeft">&#160;</td><td class="mdescRight">Start msb address mask.  <a href="group__zdma__v1__0.html#ga8b4169e9fb49a54f7c287d6ae3e57654">More...</a><br /></td></tr>
<tr class="separator:ga8b4169e9fb49a54f7c287d6ae3e57654"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr><td colspan="2"><div class="groupHeader">Channel Rate control count register bit mask</div></td></tr>
<tr class="memitem:ga88b8a953147eb61c544be509076c84e3"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__zdma__v1__0.html#ga88b8a953147eb61c544be509076c84e3">XZDMA_CH_RATE_CNTL_MASK</a>&#160;&#160;&#160;(0x00000FFFU)</td></tr>
<tr class="memdesc:ga88b8a953147eb61c544be509076c84e3"><td class="mdescLeft">&#160;</td><td class="mdescRight">Channel rate control mask.  <a href="group__zdma__v1__0.html#ga88b8a953147eb61c544be509076c84e3">More...</a><br /></td></tr>
<tr class="separator:ga88b8a953147eb61c544be509076c84e3"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr><td colspan="2"><div class="groupHeader">Channel Source/Destination Interrupt account count register bit mask</div></td></tr>
<tr class="memitem:gaae2ef41062c0004503031e155538ffa6"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__zdma__v1__0.html#gaae2ef41062c0004503031e155538ffa6">XZDMA_CH_IRQ_ACCT_MASK</a>&#160;&#160;&#160;(0x000000FFU)</td></tr>
<tr class="memdesc:gaae2ef41062c0004503031e155538ffa6"><td class="mdescLeft">&#160;</td><td class="mdescRight">Interrupt count mask.  <a href="group__zdma__v1__0.html#gaae2ef41062c0004503031e155538ffa6">More...</a><br /></td></tr>
<tr class="separator:gaae2ef41062c0004503031e155538ffa6"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr><td colspan="2"><div class="groupHeader">Channel debug register 0/1 bit mask</div></td></tr>
<tr class="memitem:ga0876c52b246b078b952127de1c6db4e7"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__zdma__v1__0.html#ga0876c52b246b078b952127de1c6db4e7">XZDMA_CH_DBG_CMN_BUF_MASK</a>&#160;&#160;&#160;(0x000001FFU)</td></tr>
<tr class="memdesc:ga0876c52b246b078b952127de1c6db4e7"><td class="mdescLeft">&#160;</td><td class="mdescRight">Common buffer count mask.  <a href="group__zdma__v1__0.html#ga0876c52b246b078b952127de1c6db4e7">More...</a><br /></td></tr>
<tr class="separator:ga0876c52b246b078b952127de1c6db4e7"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr><td colspan="2"><div class="groupHeader">Channel control2 register bit mask</div></td></tr>
<tr class="memitem:gaca1442dbc95787a8aaa20b1f8640a85a"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__zdma__v1__0.html#gaca1442dbc95787a8aaa20b1f8640a85a">XZDMA_CH_CTRL2_EN_MASK</a>&#160;&#160;&#160;(0x00000001U)</td></tr>
<tr class="memdesc:gaca1442dbc95787a8aaa20b1f8640a85a"><td class="mdescLeft">&#160;</td><td class="mdescRight">Channel enable mask.  <a href="group__zdma__v1__0.html#gaca1442dbc95787a8aaa20b1f8640a85a">More...</a><br /></td></tr>
<tr class="separator:gaca1442dbc95787a8aaa20b1f8640a85a"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga90faf95a70486b3e9f1782f2e7a89767"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__zdma__v1__0.html#ga90faf95a70486b3e9f1782f2e7a89767">XZDMA_CH_CTRL2_DIS_MASK</a>&#160;&#160;&#160;(0x00000000U)</td></tr>
<tr class="memdesc:ga90faf95a70486b3e9f1782f2e7a89767"><td class="mdescLeft">&#160;</td><td class="mdescRight">Channel disable mask.  <a href="group__zdma__v1__0.html#ga90faf95a70486b3e9f1782f2e7a89767">More...</a><br /></td></tr>
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<tr class="memitem:gadf9417e895645aaec67c6985b8c6f5eb"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__zdma__v1__0.html#gadf9417e895645aaec67c6985b8c6f5eb">XZDMA_WRITE_TO_CLEAR_MASK</a>&#160;&#160;&#160;(0x00000000U)</td></tr>
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